Although metal-oxide-silicon field-effect transistors (MOSFETs) are fabricated within a common silicon substrate, they must nevertheless be electrically isolated from one another. Once isolated, the MOSFETs can then be interconnected to create specific circuitry configurations.
MOSFETs are said to be "self-isolated;" that is, as long as the source-substrate and drain-substrate pn junctions are held at reverse bias, drain current is due only to current flow from source to drain through a channel under the gate. However, the conducting lines used to interconnect metal-oxide-semiconductor (MOS) transistors often form gates of parasitic MOS transistors within the common silicon substrate, with the oxide beneath them forming an undesired gate oxide. To isolate MOSFETs, therefore, it is necessary to prevent the formation of channels in the field regions. One way to accomplish this is to utilize a comparatively thick field oxide layer. However, as device dimensions continue to shrink, thick field oxide regions become undesirable.
Another transistor isolation technique is to raise the dopant level in the substrate beneath the field oxide to increase the parasitic gate turn-on voltage. This is typically accomplished by ion implantation to create what are referred to in the art as "field isolation regions" or "channel stop regions." The combination of field oxide and a channel stop region can provide adequate isolation for most PMOS, NMOS and oxide-isolated bipolar integrated circuits. However, the formation of channel stop regions in certain applications is not without drawbacks.
By way of example, FIGS. 1a & 1b depict one embodiment of a metal-oxide-semiconductor field-effect transistor (MOSFET), generally denoted 10, comprised of opposing source and drain regions 12 and 14, respectively. Source region 12 and drain region 14 are isolated from each other by a trench isolation oxide 16, and are isolated from an overpassing gate 17. An appropriate blocking type implant is disposed in the area beneath trench oxide 16 to define a channel stop region 20 in a substrate 22.
The channel stop implant concentration is chosen to impair formation of the parasitic thick oxide MOSFET, while at the same time minimizing impact on the electrical characteristics of the source/drain diffusions. This can be difficult, however, since heating of a semiconductor wafer during processing after forming channel stop regions can cause the implantations to migrate towards the diffusions or into the field oxide. This difficulty tends to limit the concentration of dopant in the channel stop region. One significant application for channel stop regions has been in the formation of semiconductor memory devices.
Parallel with recent exponential growth in the use of integrated circuits has come the development of numerous types of semiconductor memory devices. More particular to the present invention, memory devices have been proposed with various types of semiconductor trench and storage capacitor constructions. This invention relates to one particular type of memory construction referred to in the art as a "merged isolation and node trench" (MINT) construction. For example, reference a commonly assigned patent to D. Kenney entitled "Semiconductor Trench Capacitor Cell With Merged Isolation and Node Trench Construction, " U.S. Pat. No. 4,801,988. Practical fabrication of such devices continues to be a significant goal of the semiconductor fabrication industry. The present invention is directed to meeting this goal.